lu.se

Electrical and Information Technology

Faculty of Engineering LTH | Lund University

Event archive

AIML@LU WS: AI & ML Technologies

Published: 2019-01-16

This sixth AIML@LU fika-to-fika workshop since May 2018 focuses on the development of the technologies that form the basis of Artificial Intelligence and Machine Learning. Possible topics to discuss are the research front for different types of AI, but also to look at different techniques for machine learning as well as different ways to access or share data.

When: 11 April at 9.30 - 15.30

Where: E:A, E-building, Ole Römers väg 3, LTH, Lund University

Tentative programme

9.30 Fika I and mingle
10.15 Introduction and update regarding the network
10.30 Keynote speaker and other presentations in plenum
12.00 Lunch, mingle and poster session
13.15 Parallel Tracks
14.30 Summary and conclusions
15.00 Fika II, mingel and poster session continued

Contact

If you have any questions, suggestions or would like to contribute to the program please contact one of:

Registration will open when the when there are details in the programme. Subscribe to the sendlist if you want to ensure to be reached by an invitation.

More AIML@LU events at http://aiml.lu.se/events/

 

 

 

When: 2019-04-11 09:30 to 2019-04-11 15:30
Location: E:A, E-building, Ole Römers väg 3, LTH, Lund University
Contact: Jonas.Wisbrant@cs.lth.se


 


How to keep ESS running on time - Digit@LTH seminar by Anders Johansson, EIT

Published: 2019-01-08

Karta: Ole Römers Väg 3 in Lund, E:2358Title: How to keep ESS running on time...Nytt ärende CHG0137655 har öppnats för dig

Speaker:  Anders Johansson, Associate Professor at department of Electrical and Information Technology, LTH, Lund University

Location:  E-huset, Ole Römers väg 3. Start in EIT Lunch-room (E:2328)

Abstract
LTH, Lund University, have been deeply involved in the development of the accelerator for ESS since its establishment. Among the activities we have designed a couple of its subsystems, such as the low-level RF system and the master oscillator. One important challenge of the design is to keep everything synchonized, where parts of it has to be accurate to within pico-seconds. The talk will present how this is done, and how it is connected to the systems that have been designed at LTH.

Bio:
Anders J Johansson was born in Malmö, Sweden, in July 1968. He received the Masters, Lic. Eng. and Ph.D. degrees in electrical engineering from Lund University, Lund, Sweden, in 1993, 2000 and 2004 respectively.
From 1994 to 1997 he was with Ericsson Mobile Communications AB developing transceivers and antennas for mobile phones. Since 2005 he is an Associate Professor at the department of Electroscience at Lund University.

His research interests include antennas and wave propagation for medical implants as well as antenna systems and propagation modelling for MIMO systems. One of his main research areas is now also the design and implementation of high precision control systems for linear accelerators, especially the LLRF system for the European Spallation Source.

Please register at: https://www.lth.se/digitalth/events/register/ no later than 30 Januari at 12.00

 

 

When: 2019-01-31 09:00 to 2019-01-31 10:00
Location: E-huset, Ole Römers väg 3. Start in EIT Lunch-room (E:2328) 
Contact: Jonas.Wisbrant@cs.lth.se


 


"Hardware/Algorithm Codesign for Energy Efficiency and Robustness: From Error-tolerant Computing to Approximate and Brain-inspi

Published: 2019-01-16

Title: Hardware/Algorithm Codesign for Energy Efficiency and Robustness: From Error-tolerant Computing to Approximate and Brain-inspired Computing

Speaker: Dr Abbas Rahimi, ETHZ

E:2311, E-huset; ole Römers väg 3Place: E:2311, The department of Electrical and Information Technology, E-building, Ole Römers väg 3, LTH, Lund University

Date and time: Tuesday, January 22, 2019, at 15:15

Abstract: Scaling model of semiconductors has been immensely successful in providing exponentially increasing computational performance at an ever-reducing cost and energy footprint. Underlying this evolution is a set of well-defined abstraction layers, starting from robust switching devices to a scalable and stored program architecture, which is Turing complete. Unfortunately, this abstraction chain is being challenged as scaling continues to nanometer dimensions. Maintaining the current deterministic computational model ultimately puts a lower bound on the energy scaling, set in place by uncertainty (arising from process variations, temporal changes, and data statistics). On the other hand, the nature of computation itself is changing with data and learning-based paradigm taking primacy. Both these trends force us to rethink functionality to cope with uncertainty by adopting energy-efficient computational approaches that are inherently robust to uncertainty and ?approximate? in nature.

We entail the formulation, analysis, and development of a unified hardware/software environment that addresses the challenge of uncertainty in deeply scaled CMOS processes. Specifically, we devise codesigned methods to predict and prevent, detect and correct, and opportunistically accept impact of uncertainty and the resulting errors at many layers in the system abstraction. This discussion naturally leads to use of these methods into area of approximate computing where errors and approximations are becoming acceptable as long as the outcomes have a well-defined statistical behavior. Going one step further, we take inspiration from the very size of the brain?s circuits, to compute with points of a hyperdimensional (HD) space that thrives on randomness and mediocre components. HD computing provides a novel look at data representations (holographic and pseudorandom HD vectors), associated operations, and materials and substrates that enable them. This novel computing paradigm is closely intertwined with properties of emerging monolithically 3-D integrated and nonvolatile nanotechnologies. This synergy enables codesigned solutions to overcome large variability in both data and computing platform leading to fast learning and robust decision making with extreme energy efficiency. This offers a unique opportunity for the next-generation nanoscalable fabrics especially for cognitive and perceptive applications.

About the speaker: Abbas Rahimi received his B.S. in computer engineering from the University of Tehran, Tehran, Iran (2010) and his M.S. and Ph.D. in computer science and engineering from the University of California San Diego, CA, USA (2015), followed by two years postdoctoral research in the Department of Electrical Engineering and Computer Sciences at the University of California Berkeley, Berkeley, CA, USA. Dr. Rahimi has been awarded an ETH Zurich Postdoctoral Fellowship, and subsequently joined the Department of Information Technology and Electrical Engineering at ETHZ in June 2017. He is also affiliated with the Berkeley Wireless Research Center. His research interests include embedded systems and software, brain-inspired computing, approximate computing, and massively parallel integrated architectures with an emphasis on improving energy efficiency and robustness. His doctoral dissertation has received the 2015 Outstanding Dissertation Award in the area of ?New Directions in Embedded System Design and Embedded Software? from the European Design and Automation Association (EDAA). He has also received the Best Paper at BioCAS (2018), BICT (2017), and the Best Paper Candidate at DAC (2013).

When: 2019-01-22 15:15 to 2019-01-22 15:15
Location: E:2311, The department of Electrical and Information Technology, E-building, Ole Römers väg 3, LTH, Lund University
Contact: ove.edfors@eit.lth.se


 


ELLIIT Distinguished Lecture: Millimeter-wave high-datarate wireless communication using beamforming by Prof. Piet Wambacq

Published: 2018-11-30

Title: Millimeter-wave high-datarate wireless communication using beamforming

Speaker:  Prof. Piet Wambacq

Place: E-building, Ole Römers väg 3,  E:2311, LTH, Lund University

When: December 13th, 2018, 14.15

Abstract:
Millimeter-wave high-datarate wireless communication using beamforming (Piet Wambacq)
In the past ten years, the speed increase of CMOS thanks to the downscaling in the past ten years, together with the allocation of unlicensed spectrum around 60 GHz, has given rise to much research worldwide on mm-wave IC design in CMOS. The frequency band between 57 GHz and 66 GHz is intended for high datarate wireless communication using RF bandwidths of more than 1 GHz. The commercial deployment of mm-wave ICs takes more time than expected, partially due to the design challenges caused by the high operating frequency, which is more than ten times higher than the commercial ICs for the most widely used wireless communication standards, which operate below 6 GHz. To relax the high path loss at mm-wave frequencies in the link budget of wireless transceivers, these transceivers contain, next to the classical functionality of radios, beamforming functionality. This talk will explain the basics of beamforming together with several implementations of the beamforming control in the analog part of the transceivers. Further, most important bottlenecks of mm-wave radio architectures such as phase noise and power efficiency are addressed and several solutions are discussed. 
 
About the speaker:
Piet Wambacq  received the M.Sc. degree in electrical engineering and Ph.D. degree from the Katholieke Universiteit Leuven, Leuven, Belgium, in 1986 and 1996, respectively. He joined IMEC, Leuven, Belgium in  1996 as a Principal Scientist and he is now a Distinguished Member of Technical Staff, working on IC design in various technologies for wireless applications. Since 2000 he is a Professor with the Vrije Universiteit Brussel (VUB), Brussels, Belgium. He has authored or co-authored three books and more than 250 papers in edited books, international journals and conferences. He has been an associate editor of the IEEE Transactions on Circuits and Systems - Part 1 from 2002 to 2004. He was the co-recipient of the Best Paper Award at the Design, Automation and Test Conference (DATE) in 2002 and 2005, the EOS/ESD Symposium in 2004 and the Jan Van Vessem Award" for "Outstanding European Paper" at ISSCC 2015. He was a member of the program committee of the DATE conference from 2000 to 2007. He currently chairs the RF subcommittee of ISSCC and of ESSCIRC. He is a senior member of IEEE and Distinguished Lecturer of The Solid-State Circuits Society of IEEE.

When: 2018-12-13 14:15 to 2018-12-13 14:15
Location: E-building, Ole Römers väg 3,  E:2311, LTH, Lund University
Contact: markus.tormanen@eit.lth.se


 


PhD dissertation by Therese Forsberg: Efficient mm-Wave Transmitter Design in CMOS Technology

Published: 2018-10-30

Author: Therese Forsberg

Thesis title: Efficient mm-Wave Transmitter Design in CMOS Technology.

Main supervisor: Markus Törmänen

Faculty opponent: Piet Wambacq from IMEC

When: 13 December at 9:15

Loaction: Lecture hall E:1406, building E, Ole Römers väg 3, Lund

Thesis for download

Thesis abstract:
An increasing demand of higher data rates in wireless communication forces the industry to look to higher frequencies to find the required bandwidths. This thesis is about analog transmitters in CMOS for millimeter-wave communication, and it focuses on improving power amplifiers and frequency generation circuits, and increase their efficiency. This thesis starts with an introduction to millimeter-wave transmitters in CMOS, standards and beamforming. It then continues with a brief introduction to millimeter-wave power amplifier design and design of local oscillators at millimeter-wave frequencies. The last part of the thesis consist of six papers, which present eleven manufactured and measured millimeter-wave circuit designs. Paper I presents a two-stage, 65-nm CMOS, Class-A PA for the 60-GHz band. It employs capacitive cross-coupling neutralization for higher differential isolation and gain, without the need to increase the power consumption. It achieves 18.5 % peak-added-efficiency. Paper II presents a varactorless VCO in 65 nm CMOS, operating in the 60-GHz band. In paper III, the efficiency of the popular source-node filtering technique for improved phase-noise performance is investigated through measurements of two same-chip 60-GHz VCOs in FD-SOI CMOS. The filtered VCO achieves a state-of-the-art figure-of-merit of -187.3 dBc/Hz. Paper IV presents two FD-SOI CMOS VCOs for the 30-GHz and the 60-GHz band, that achieve ultra-low power consumption, also at full supply voltage. In paper V, a phase-locked loop in 28-nm FD-SOI CMOS for 5G transceiver systems is proposed. Its VCO operates at around 55 GHz. The paper describes the disadvantages of using a too high input reference frequency, but also proposes a new architecture that handles the increased settling time by mode-switching. It also includes a novel charge-pump current-mismatch mitigation technique based on feedback, and a novel wideband and low-power injection-locked divide-by-three circuit. The phase-locked loop consumes only 10 mW of power, has an integrated jitter of 176 fs, and demonstrates a state-of-the-art figure-of-merit of -245 dB. Paper VI describes a wideband injection-locked divide-by-two circuit in 28-nm FD-SOI CMOS. It achieves a locking range of 30 % at the low power consumption of 4.3 mW.

Thesis for download

When: 2018-12-13 09:15 to 2018-12-13 09:15
Location:  Lecture hall E:1406, building E, Ole Römers väg 3, Lund


 


Page Manager: |